For sixty years, chipmakers have made computers faster by making transistors smaller and packing more of them onto a flat slice of silicon. That approach is now running into hard physical limits. IBM says it has a way forward — not by going smaller, but by going up.

Building upward

The company has unveiled a research prototype of what it calls a "nanostack" design, which builds transistors in layers stacked on top of one another rather than spread across a single surface. IBM and others have likened it to a block of flats: instead of a sprawling single-story layout, the residents are stacked floor by floor, freeing up the ground beneath, IBM said in its announcement.

Technically, the approach pairs two types of transistor vertically — a "complementary field-effect transistor," or CFET — and moves power delivery to the back of the chip to free up space on the front for logic. IBM describes the result as a sub-1-nanometer class of chip, a scale approaching the size of individual atoms.

What IBM claims

IBM says the prototype packs on the order of 100 billion transistors onto a chip roughly the size of a fingernail — about double the density of the 2-nanometer chip it unveiled in 2021. The company claims the design can deliver up to 50% more performance, or alternatively around 70% better energy efficiency, compared with that 2-nanometer generation, as reported by EE Times. Those are IBM's own figures, drawn from laboratory testing rather than mass production.

The timing matters because demand for computing power — especially for energy-hungry artificial-intelligence systems — is rising fast, making efficiency gains commercially and environmentally valuable.

Promise, and skepticism

Some analysts were enthusiastic. Dan Hutcheson of the firm TechInsights called the technology potentially "transformational" and suggested it could add years to the industry's roadmap, MIT Technology Review reported.

Others were more cautious. Stacking transistors raises hard engineering problems: heat builds up in densely packed vertical layers and has fewer routes to escape, and the ultra-thin insulation between layers can make transistors harder to switch off cleanly. Manufacturing yield is another worry — if a flaw in either stacked layer ruins the whole chip, defect rates and costs could climb. Independent experts noted that IBM's plan is more ambitious than the stacking efforts already pursued by rivals such as Samsung and Intel, which raises both the potential payoff and the risk.

A long road to silicon

It is important to stress what this is: a research milestone, not a product. IBM demonstrated that the basic physics works in the lab; turning that into mass-produced processors would require years of engineering, enormous capital investment, and next-generation manufacturing tools that are not yet widely deployed. IBM no longer runs its own chip factories, so commercialization would depend on a manufacturing partner.

IBM has said it is targeting a production pathway within about five years and frames the nanostack as a way to keep meaningful chip scaling alive into the 2040s. Whether it gets there will depend on solving manufacturing challenges that, for now, do not have proven solutions at commercial scale. What the announcement does offer is a credible technical direction at a moment when the industry has been searching for one.